Optimised cryptographic solution for home automation – New Electronics
OberonÃ¢Â€Â™s cryptographic code, a key component of its OberonHAP product, has been ported to the Cortus APS3RP 32-bit IP core.
The company has developed a number of novel algorithm combinations, and written critical parts in assembly language for high performance. The software is, according to the company, typically three times as fast as a good implementation in C. As a result OberonHAP is now able to make secure home automation feasible even on low-power, low-cost 32-bit microcontroller cores for ASICs.
Ã¢Â€ÂœHome automation is a key application area for Cortus,Ã¢Â€Â says Michael Chapman, CEO and President of Cortus, Ã¢Â€ÂœSo we are delighted to see the first steps completed in making OberonÃ¢Â€Â™s code available for Cortus licensees.Ã¢Â€Â He adds, Ã¢Â€ÂœWith the growing connectivity of home devices, security is essential and Cortus welcomes teaming up with Oberon microsystems in this field.Ã¢Â€Â
OberonHAP implements the following cryptographic algorithms for pairing, authentication and encryption:
- Secure Remote Password (SRP)
For an integrated circuit with the processor core running at 50 MHz, the cryptographic processing of the SRP algorithm Ã¢Â€Â“ which is required once in the lifetime of a home automation device Ã¢Â€Â“ now takes under five seconds. Cryptographic processing during opening of a session between a device and a smartphone takes less than 100 milliseconds. RAM requirements were brought down to a low of just 2.5 KB.
Ã¢Â€ÂœThe combination of OberonÃ¢Â€Â™s optimised cryptographic code and the APS3RP results in very good performance even on low-cost, low power devicesÃ¢Â€Â, said Cuno Pfister, managing director of Oberon microsystems AG.
The APS3RP is an enhanced performance version of the widely-deployed APS3R and provides a single cycle parallel multiplier. It has a Harvard architecture and a 3-stage pipeline. The Cortus family of APS processors offers a wide choice of computational performance and system complexity for embedded SoCs. All cores interface to CortusÃ¢Â€Â™ peripherals including Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG. They also share the simple vectored interrupt structure which ensures rapid, real time interrupt response, with low software overhead.
The APS toolchain and IDE (for C and C++) is available to licensees free of charge, and can be customised and branded for final customer use. Ports of various RTOSs are available such as FreeRTOS, Micrium Ã‚ÂµC/OSII, Micrium Ã‚ÂµC/OSIII and Blunk TargetOS.To date well over 900 million devices have been manufactured containing Cortus processor cores.
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